1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device.
2. Description of Related Art
With miniaturization progressing, there has been a demand for an increase in the surface area of a capacitor electrode for each memory cell in a memory device, for example, a DRAM in a generation with a 50-nm design rule (F value) or any subsequent generation. A common method for forming a capacitor electrode with a large surface area includes forming a conductive film in a small opening with a high aspect ratio and processing the conductive film into a capacitor electrode.
However, a higher aspect ratio makes the controllable formation of a small opening more difficult. That is, an attempt to form an opening with a high aspect ratio by normal dry etching may result in a phenomenon called etch stop. In this case, forming a hole with a desired shape is difficult particularly at the bottom of the opening.
In case of forming a contact plug with a high aspect ratio, a similar problem may occur when an opening (contact hole) with a high aspect ratio is formed.
A proposed method for forming a contact plug includes forming a lower layer-side plug and forming an upper layer-side plug on the lower layer-side plug to produce a plug stack structure. Such a plug stack structure is described in, for example, Japanese Patent Laid-Open Nos. 2005-332978 and 2004-311918.
As described above, disadvantageously, forming an opening with a high aspect ratio is not easy. Furthermore, the method of forming a stack structure as described above may increase the number of steps required to form the target structure. This may prevent semiconductor devices from being inexpensively manufactured.